Some examples of the present inventive concepts relate to a semiconductor memory device, and, more particularly, relate to a semiconductor memory device of a stacked chip structure in which a plurality of memory dies are stacked.
A dynamic random access memory DRAM may be implemented in the form of a multi-chip package to increase memory capacity. That is, the multi-chip package denotes a package in which a plurality of memory dies are stacked. For example, the plurality of memory dies may have a substrate interposed therebetween and may receive signals provided from a controller. This structure may be called, for example, a dual-rank structure.
As a transmission speed increases, a swing width of a signal exchanged between the controller and the DRAM gradually decreases to minimize a delay time taken to transmit the signal. As the swing width decreases, the influence of an external noise on the signal increases, and reflection of the signal according to impedance mismatching at an interface terminal becomes critical. When the impedance mismatching occurs during transmission of the signal, a signal integrity issue arises. A decrease in the signal integrity makes it difficult to rapidly transmit the signal and causes an error during an access operation including a write operation and a read operation of the DRAM.
Accordingly, in a DRAM die of a receiving side, an impedance matching circuit referred to as “on-die termination” or “on-chip termination” is mounted near a pad in a memory die. Generally, in an on-die termination scheme, a source termination is made in a device, for example, a controller, of a transmitting side. In a memory, for example, memory die, of a receiving side, a parallel termination is made by a termination circuit connected in parallel, with respect to a reception circuit connected to an input pad.